HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities
In the post-Moore's era, compute-in-memory (CIM) techniques are promising to break the memory wall. In particular, SRAM-based CIMs (SRAM-CIMs) have attracted widespread attention owing to its good scalability with advanced process. At present, a rich variety of works focus on energy-efficiency improvement by either designing different bit-cell structures or optimizing circuit/chip architectures. However, owing to the CIM's primitive property to store one of the operands in the memory bit-cells, substantial computing resource is wasted by suspension during the operands loading procedure. In this article, a high-throughput SRAM-CIM (HiT-CIM) architecture with simultaneous weight loading and computing capabilities is proposed by integrating on-chip nonvolatile MRAM (magnetic random-access memory). Meanwhile, both the mainstream current-domain and charge-domain SRAM bit-cell structures are optimized to support such an architecture. Furthermore, a reconfigurable fully-pipelined MRAM is designed to provide fast data loading in HiT-CIM, which can finetune weight loading strategy rapidly for different neural network models. Afterwards, an optimal evaluation and configuration strategy is proposed to improve the macro-level performance by considering the key components and parameters in terms of SRAM array, ADC, MRAM structure and frequency. Finally, the HiT-CIM's feasibility is verified under a 40-nm foundry's process. The results show that a multiple-fold speed improvement can be obtained on VGG19, ResNet18 and MobileNetV1, respectively. In specific, the area efficiency of HiT-CIM on VGG19 achieves 1124 GOPS/mm<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> and 1880.12 GOPS/mm<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula> for the current-domain and charge-domain SRAM-CIMs, respectively. Up to 5.3× improvement is realized compared with prior works.
Authors
- Junzhan Liu (ORCID: https://orcid.org/0009-0008-0295-5309)
- Sifan Sun
- He Zhang (ORCID: https://orcid.org/0000-0001-9501-0612)
- Lichuan Luo
- Ran Liang (ORCID: https://orcid.org/0000-0001-9858-7361)
- Wang Kang (ORCID: https://orcid.org/0000-0002-3169-6034)
- Liang Zhang (ORCID: https://orcid.org/0000-0001-9233-5972)
- Weisheng Zhao (ORCID: https://orcid.org/0009-0003-1386-4887)
Institutions
- Jinling Institute of Technology (CN)
- Beihang University (CN)
Publication Details
- Journal
- IEEE Transactions on Emerging Topics in Computing
- Published
- 2024-10-09
- DOI
- https://doi.org/10.1109/tetc.2024.3471176
- Citations
- 3
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 1.47