A Semi-Automated Sizing Tool for CMOS Analog Building Blocks Integrated into EDA Environment

The integrated circuits - digital, analog, or mixed-signal - are designed and verified through the use of circuit simulators before being reproduced in real silicon. Analog integrated circuits exploit the physics of the manufacturing process, manipulating precise quantities such as voltages, currents, charges, and continuous ratios of parameters like resistance and capacitance. Unlike digital circuits, there are not many design automation tools for analog ICs. In this context, this paper presents a sizing tool for CMOS transistors, in order to assist the design of integrated circuits in sub-micrometric technologies. This tool is based on a set of subroutines implemented using Python and Cadence SKILL programming languages with a command line interface (CLI) to the Cadence Spectre simulator. The semi-automated sizing tool presented can be used to explore the transistor size considering the small-signal parameters and bias-point information. This tool is detailed in this work, and the design results of a common-source amplifier and a negative transconductor are presented considering 180 nm and 65 nm CMOS fabrication processes.