Chimera: A co-simulation framework combining with gem5 and FPGA platform for efficient verification

To accommodate the requirements of increasingly diverse applications, the scale of System-on-Chip (SoC) has extended beyond single-chip, evolving towards chiplets. This expansion is accompanied by a significant increase in the number of functional IPs. Each new IP undergoes a lengthy development process to meet expected performance and ensure compatibility with existing SoCs. The conventional development process is generally divided into several distinct stages, including architecture exploration, RTL development, standalone testing, and integration verification. As IP complexity escalates and coupling with the software stack becomes intricate, the standalone testing phase fails to guarantee complete IP functionality. This deficiency leads to extended development periods and necessitates numerous iterative design revisions during the integration verification phase, hindering the efficiency of IP integration into SoC. In this paper, we introduce Chimera, the first co-simulation framework that combines ESL simulators and the FPGA platform. The framework streamlines the conventional development process, providing a direct approach to architecture exploration and integration verification of a Register-Transfer Level (RTL) IP within an SoC running on the gem 5 simulator. We propose three optimizations including an optimistic synchronization mechanism, batch processing, and dataflow merging to enhance the efficiency of Chimera. Our experimental results demonstrate that Chimera can sustain co-simulation speeds comparable to the speed of the standalone gem5 simulator within typical system configurations. Furthermore, Chimera outperforms the state-of-the-art co-simulation framework, achieving up to a $20 \times$ performance improvement.