Enabling Programmable Data Planes with C++ and High-Level Synthesis for Custom Packet Forwarding

This paper proposes a novel approach to realize programmable data plane descriptions into wire-speed performance hardware. We achieve this objective by combining a custom C++ model for describing packet forwarding devices with generic vendor-agnostic high-level synthesis tools. We compare three packet-forwarding devices with the P4-NetFPGA/NetFPGA-SUME canonical design, considering throughput, latency, and resource usage. Our findings demonstrate the viability of describing packet-forwarding devices within the suggested workflow while providing improved throughput, latency, and resource usage. Results can help designers reach fast time-to-markets with more efficient hardware and pave the way for better PDPs.