Gate Voltage Dip as a New Indicator for Online Health Monitoring of SiC MOSFETS

Due to the poor quality of the silicon carbide / silicon dioxide interface realization and their thin gate oxide layer, SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s are more susceptible to charge-trapping mechanisms than silicon <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s. These phenomena are amplified over time, resulting in decreased transistor performance and increased losses. To monitor this aging mechanism, an analog method is proposed to extract a newly discovered health indicator from the gate voltage (V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub>) waveform. This is accomplished by slowing down a specific turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> using a dual-channel active gate driver. The online health monitoring method is then experimentally validated on a 1200 V-36 A SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> in both no-load and pulsewidth modulation conditions.