A Divide-by-1.5/2 Prescaler Utilizing Double Data Rate Technique

Half-integer step dual-modulus prescalers effectively reduce phase noise in Fractional-N frequency synthesizers by minimizing the feedback divider quantization error. Traditional fractional frequency dividers offer limited maximum operating frequency and high power consumption. Novel divide-by-1.5/2 prescaler circuits based on the double data rate (DDR) technique are proposed in this work. Simulation results of 65 nm CMOS designs demonstrate that the DDR technique can lower power consumption by up to 32% and increase up to 4.1x the maximum operating frequency when compared to conventional prescalers based on dual-edge triggered flip-flops. Additionally, an original balanced-DDR version is proposed that greatly suppresses the output period modulation observed in the other topologies.