A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm

In this article, we introduce a new dynamically biased ring amplifier that is tolerant to mismatch and PVT variation without requiring bias calibration, and we verify it in a 12-bit 400-MS/s pipelined-SAR analog-to-digital converter (ADC), fabricated in an 8-nm FinFET process. Our novel ring amplifier solves the biasing issues inherent in conventional ring amplifiers while maintaining the benefits of high gain, slew-based charging, and nearly rail-to-rail output swing. We also propose a technique to enhance the DC accuracy of a switched-capacitor common-mode feedback (CMFB) without consuming additional power, which we named feedback voltage sampling CMFB. Furthermore, we introduce a full-scale matching residue amplification technique for the prototype pipelined-SAR ADC to utilize the top-plate input sampling for the first-stage SAR ADC, resulting in faster and lower power conversion. The prototype ADC demonstrates the robustness of our dynamically biased ring amplifier to mismatch and PVT variation without any interstage gain, bias, or reference calibration, and achieves 64.4-dB SNDR and 77.6-dB SFDR for a low-frequency input while consuming 2.08 mW. This measured performance is equivalent to Walden and Schreier FoMs of 3.8 fJ/conversion<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula>step and 174.2 dB, respectively.