Leveraging HBM2 for Accelerating k-mer Counting with oneAPI on FPGAs

Counting substrings of an arbitrary length k (k-mers) is the single most time-consuming step of de novo genome sequencing. Sequencing machines generate large quantities of data $(\gt100$ s of GBs per genome), which need to be processed using frequent memory accesses into data structures considerably larger than available cache, leading to a memorybound runtime. Stemming from the gap between processor and memory speed, this bottleneck requires alternative architectures. Recent FPGA devices, equipped with on-chip High-Bandwidth Memory (HBM), enable custom architectures to employ high-capacity, high-bandwidth memory to address memory-bound tasks. This research investigates accelerating k-mers counting with one such device, the BittWare 520N-MX, a Stratix 10 FPGA with 16 GB of on-chip HBM2. The architecture was designed using Intel’s oneAPI, which enables high-level synthesis for FPGA programming. The accelerator architecture was able to leverage inherent parallelism in the algorithm via the multiple parallel hash functions, along with partitioning data structure across multiple memory banks, and employing multiple independent parallel processing pipelines on the device to maximize throughput. The accelerator achieved $42.67 \mathrm{M} \boldsymbol{k}$-mers per second, $2.80 \times$ more than the throughput-optimized CPU version and $4.31 \times$ more than the original CPU app. Despite this speedup, the architectures saw diminishing returns when attempting to incorporate additional HBM2 banks. OneAPI was able to achieve speedup over the CPU using the FPGA and emerging memory, but it’s somewhat limited in its current scaling capabilities.