ATP-Optimized Four-Term Karatsuba Multipliers for Large Integer Arithmetic on FPGAs

This work presents two methods of hardware implementation of area-time-product (ATP)-optimized four-term Karatsuba multipliers (FTKM) on Field Programmable Gate Arrays (FPGAs). This is done by eliminating the effects of complexity of sub-multiplications present at the intermediate steps of computation. Besides these, hardware implementation of the proposed work suggests that the proposed FTKM multiplication methods (FTKM-I and FTKM-II) performs better in terms of resource utilization and delay minimization compared to other existing state-of-the-art multiplication methods, irrespective of input bit lengths. Hardware implementations of the proposed FTKM methods (FTKM-I and FTKM-II) multiplication architecture are demonstrated on a Virtex-7 FPGA device in Xilinx ISE platform. Here, the hardware implementation of the proposed FTKM multipliers is carried out for 128 bits, 256 bits, 512 bits, and 1024 bits, showcasing advantages in area-time-product (ATP) over previous research. ATP serves as the Figure-of-Merit (FoM) for determining the performance of the design.