FPGA-Optimized Asymmetrical and Symmetrical Six-Term Karatsuba Multipliers

The need for efficient multiplication of large integer polynomials in contemporary cryptographic systems is crucial. This study explores six-term Karatsuba multiplication, known for its efficiency but often avoided due to complex sub-multiplications. The focus is on implementing asymmetrical and symmetrical six-term Karatsuba Multiplication (ASTKM-I, ASTKM-II, SSTKM-I, and SSTKM-II) for enhanced speed and hardware utilization. To evaluate performance, Area-Time-Product (ATP) is calculated and compared with conventional asymmetrical and symmetrical six-term Karatsuba multiplication (CASTKM and CSSTKM) and state-of-the-art approaches. Hardware implementations on a Virtex-7 FPGA device in Xilinx ISE platform show that the best proposed method (ASTKM-II) outperforms other designs, being 17.983%, 79.361 %, 33.439%, 3.536%, 41.494%, 5.975%, and 9.343% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), CASKTM, ASKTM-I, CSSTKM, SSTKM-I, and SSTKM-II, respectively, for 1024-bit inputs.