FPGA Based LSTM Network: A Power and Resource Optimized Solution for Edge Computing

LSTM, a recurrent neural network (RNN) well-suited for sequential data tasks, often incurs computational expenses during training and deployment, particularly with large and intricate models. The enhancement of LSTM network performance can be accomplished through hardware acceleration. Field-programmable gate arrays (FPGAs), enabling custom circuit implementation, can facilitate the creation of hardware accelerators for LSTM networks, resulting in substantial speed improvements over software implementations. An LSTM network hardware accelerator was implemented on the ZedBoard, a well-known FPGA development board. Performance evaluations of this accelerator across various time series datasets were conducted. The results demonstrated that the proposed accelerator achieved speedups of up to 45x compared to the software implementation. The accelerator's performance is on par with leading LSTM accelerators implemented on other FPGA platforms. The accelerator attains a performance level of 1.203 GOP/S while operating within a power consumption of 0.235W, making it well-suited for power-constrained applications.