A Comprehensive Evaluation of Schmitt Trigger Designs in 90nm CMOS Technology

This paper presents an in-depth analysis of various CMOS Schmitt triggers utilized in the VLSI industry for mitigating noise effects. This paper conduct a comparative assessment of different CMOS Schmitt trigger designs, delving into their respective architectures and operational principles. The study includes a comprehensive discussion of the design intricacies of each Schmitt trigger architecture. Furthermore, we present a comparative evaluation of these architectures based on key parameters such as hysteresis width, power consumption, delay, and noise. Our findings reveal that no single architecture satisfies all specification requirements. Consequently, we perform a comparative study focusing on widely adopted architectures in GPIO buffers. This enables designers to make informed decisions regarding the most suitable design architecture based on specific project requirements. All simulations were conducted using CADENCE Virtuoso in the Spectre simulator, employing 90nm CMOS Technology.