Comparative Analysis of Reversible Arithmetic Logic Units (R-ALU) Using Verilog

Optimizing power consumption in circuits can be facilitated by exploring reversible computing within Quantum QCA design alongside CMOS architecture design. This paper introduces a comparative examination of four Reversible Arithmetic Logic Units. Certain parameters such as number of Reversible gates utilized, Dynamic & Static power, Area (Slice Look up tables consumed/LUT), Input-Output blocks (IOB), Garbage bits, No. of Arithmetic and Logical Operations performed have been studied. Among the examined reversible arithmetic logic units, ALU-D1 stands out for its minimal dynamic and static power consumption, totaling a typical process power of 2.769 watts. Following closely is ALU_RM, with a typical process power of 3.097 watts. ALU-D1 and ALUD2 exhibit the lowest IOB count, specifically 12, and also have the least Slice LUT consumption at 4/14400. In terms of construction, ALU-D1 and ALU-D2 utilize 11 reversible gates, while ALU_RM and ALU_RUG employ 14 and 13 reversible gates, respectively. Both ALU-D1 and ALU-D2 excel in executing 18 operations each, whereas ALU_RM and ALU_RUG handle 16 operations each. In nearly all aspects, ALU-D1 and ALU-D2 outperform their counterparts, except for a higher consumption of garbage bits in their construction. The study involves the implementation of various reversible Arithmetic Logic units using Verilog in Vivado ML Edition – 2023.2 for FPGA, targeting the Zynq-7000 family of FPGAs.