Minimizing Leakage Current & Ground Rail Fluctuations in 1-Bit 8t Full Adder Circuit Using Mtcmos Techniques

Controlling leakage current and noise resistance has become crucial in the design of combinational and sequential circuits as technology moves closer to nanoscale scales. Multi-threshold CMOS is one extensively used method of addressing leakage current (MTCMOS). Nevertheless, even though the traditional MTCMOS method is good at lowering leakage current, it frequently causes variations in the ground rail while switching from low-leakage sleep mode to active mode, which affects the overall dependability of the circuit. In this case, by carefully sizing various transistors, a low-leakage eight-transistor (8T) based 1-bit complete adder is constructed. Optimisation algorithms are used to determine transistor sizes. In order to minimize leakage current even more, the improved 8 transistor full adder is subjected to a number of widely used leakage reduction approaches. Leakage current and ground fluctuation noise are compared using several widely used MTCMOS techniques. According to simulation studies, the improved 8T transistor can reduce sub-threshold current leakage by as much as 62% when used in conjunction with common MTCMOS methods.