Design of Canonical Huffman Encoder in VLSI for Data Compression

Design of Canonical Huffman Encoder is an emerging technology in Very Large-Scale Integration (VLSI). The proposed design comprises three key stages: Frequency Generation, Code Size Computing, and Sorting and Code Size Limiting. This canonical Huffman encoding approach assigns variable length codes to symbols according to their frequencies, simplifying the encoding process. This frequency data constructing a canonical Huffman tree, optimizing binary codes for symbols and effectively reducing the overall data sizes. When implemented in Verilog 2017.4, it generates encoding bits as output, representing canonical code-sizes and canonical code-words. The results indicated that the proposed architecture decreased encoding time by 46.09%. Furthermore, a reduction in area of 60% and a power saving of 70% were observed in the Huffman encoder. The hardware implementation of LZ77 encoder and dynamic huffman encoder in data compression are designed for effective implementation of GZIP compression. Above the scenario has been executed using the Nexys A7-100T Artix-7 Series FPGA Evaluation Board. GZIP, an extensively utilized compression algorithm recognized for its effective compression ratios, is targeted to achieve a compression ratio of 88.92%.