Performance Evaluation of Adiabatic Logic-Based Multiplexer and Full Adder Circuits for Ultra-Low Power Applications

In the current scenarios, power dissipation is the primary concern when designing a VLSI circuit. The need for logic devices that use minimal power is continually growing, and adiabatic logic provides an ideal answer to this problem. The adiabatic technique is a prominent approach that significantly reduces power dissipation by recycling the stored charge at different nodes. Since the multiplexer plays a significant role in data transmission, whereas a full adder is needed for many arithmetic operations, an efficient low-power design circuit is required for these operations. This paper presents a comprehensive analysis of traditional CMOS, traditional Positive Feedback Adiabatic Logic (PFAL), and various modified PFAL circuits for 2:1 multiplexer and full adder circuits. These circuits were implemented and simulated by 90nm and 45nm technology using the Cadence virtuoso EDA tool, and the average power dissipation and performance for each of the circuits were observed. This design showcased in this research holds potential for various applications, such as portable devices, low-frequency operating systems, battery-powered systems, and high-performance computing systems.