Design of Vertical Double Source TFET for Low Power Applications

The design and analysis of a VDSTFET optimized for low power applications are presented in this paper. TFETs have attracted a lot of attention lately because of their ability for resolving problems with energy efficiency in contemporary integrated circuits. But ordinary TFET designs challenge to achieve low off-currents as well as high on-currents, which are essential for low power operations. This work suggests a unique VDS-TFET design that is low power application-optimized in response. By utilizing a vertical channel layout with two source regions, the suggested VDS-TFET design improves carrier injecting performance and electrostatic control. The design provides enhanced efficiency measures, such as steeper sub-threshold slopes, lower leakage currents, and increased oncurrents—all crucial for low power operation— through extensive devices simulations and improvement methodologies.