Low Power and High -Speed Sense Amplifier Design For 6T SRAM

A new model of a current sense amplifier has been proposed. This circuit is more efficient because of its better performance in operational parameters such as: power and time delay. Using a general model of static random-access memory consisting of six -transistors (6T), the proposed model of sense amplifier has displayed more efficient operation than the existing current sense amplifier models. Cadence Virtuoso software is employed for simulation experiments. In terms of power consumption, the proposed circuit performed 99.5% better than the traditional Alpha Latch-based sense amplifier and 1.08% betterthan the traditional current conveyor-based sense amplifier circuit. The proposed sense amplifier has overcome propagation delays of 83.38% and 99.99% respectively in the current conveyor and the Alpha Latch models.