Self-sufficient ESD Solution for Fail-safe I/O Design in FinFET Technology

A silicon validated novel snapback ESD design to provide self-sufficient ESD protection for fail-safe I/O in FinFET technology is introduced. The self-sufficient ESD provides I/O to ground, I/O to power and power to ground discharge paths in single ESD cell to efficiently suppress ESD clamping voltage in all ESD zapping combinations. Low-ESD clamping voltage benefit of self-sufficient snapback ESD can relax fail-safe I/O victim design requirement to size-down fail-safe I/O and reduce power clamp requirement in I/O clusters to reduce I/O standby leakage.