Design and Evaluation of FPGA-Optimized Asymmetrical Three-Term Karatsuba Multipliers

This paper focusses on FPGA-based optimized implementations of asymmetrical three-term Karatsuba multiplication (AThTKM) architecture. Two multiplications, AThTKM-I and AThTKM-II, are proposed to implement AThTKM, aimed at enhancing the critical path and circuit area. The performance of the proposed design methods is assessed by computing the Area-Time-Product (ATP) and comparing it with conventional asymmetrical three-term Karatsuba multiplication (CAThTKM) and traditional schoolbook multiplication (SBM). Hardware implementations of both proposed AThTKM multiplication archi-tectures are conducted on Virtex-7 FPGA Board using Xilinx ISE platform. The area-time-product (ATP) performance of the proposed AThTKM-I, based on ΔATP<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>, is better by 22.091%, 80.394%, 32.988%, and 5.277% than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), and CAThTKM, respectively, for 1024-bit inputs. Similarly, the performance of the proposed AThTKM-II, based on ΔATP<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, is better by 17.751%, 79.302%, 29.254%, and -5.571% than Direct Multiplication (DM), Traditional SBM, and CAThTKM, respectively, for 1024-bit inputs. However, comparing both proposed methods of AThTKM (AThTKM-I and AThTKM-II), it can be inferred that AThTKM-II is 0.365%, 3.720%, and 5.277% better than AThTKM-I for 128 bits, 512 bits, and 1024 bits, respectively, while AThTKM-I is 1.080% better than AThTKM-II for 256 bits, respectively, thus demonstrating its area-time-product efficiency.