FPGA-Optimized Seven-Term Karatsuba Multipliers for Large Integer Arithmetic

Efficient multiplication of large integer polynomials is essential in modern cryptographic systems. This research delves into the seven-term Karatsuba multiplication method, renowned for its efficiency but often overlooked due to its intricate sub-multiplications. The study concentrates on implementing both asymmetrical and symmetrical versions of seven-term Karatsuba Multiplication (ASeTKM-I, ASeTKM-II, SSeTKM-I, and SSeTKM-II) to enhance speed and hardware utilization. To assess performance, the Area-Time-Product (ATP) metric is computed and compared against conventional asymmetrical and symmetrical seven-term Karatsuba multiplication techniques (CASeTKM and CSSeTKM), as well as contemporary methodologies. Hardware implementations on Virtex-7 FPGA device in Xilinx ISE platform reveal that the most effective proposed method (ASeTKM-I) surpasses other designs. It exhibits superiority, being 19.443%, 79.728%, 39.632%, 5.346%, 37.796%, 6.720%, and 2.616% better than Direct Multiplication (DM), Traditional Schoolbook Multiplication (Traditional SBM), CASeKTM, PASeKTM-II, CSSeTKM, PSSeTKM-I, and PSSeTKM-II, respectively, for 1024-bit inputs.