FPGA Implementation of Area Efficient Adaptive Filter for Low Computational Complexity

The proposed work is based on the reduction of computational complexity as well as chip area for an adaptive filter architecture using the sign-sign least mean square (LMS) algorithm. The computations required for the sign-sign LMS algorithm have been reduced significantly compared to the standard least mean square (LMS) algorithm as the proposed method does not require any multiplier in the weight update loop. We have designed two filters for our proposed design, the first being a normal FIR filter and the other pipelined FIR filter, which uses pipelining techniques to achieve better throughput and the weights of the filter updates according to the proposed algorithm. The synthesis and implementation of the design have been done on the Xilinx Vivado tool using Verilog hardware description language (HDL), and the utilization of hardware resources and timing reports have been compared for both cases and found that minimal increment in the hardware resources, the maximum frequency of operation of the filter can be increased. The designs are being realized using Xilinx Artix - 7 FPGA.