Extending ESD Network Capability to EOS and Overvoltage Protection

Physical principles for on-chip solutions with combined ESD, EOS and overvoltage protection (OVP) are presented. The proposed main approach is an upgrade of the conventional ESD protection network components, with extra EOS and OVP capability using additional small footprint clamp and device add-ins. An insight on physical electrothermal processes for EOS stress is presented. The methodology of on-chip performance validation using TLP and long pulse measurements is discussed.