System CDM Modeling for High-Speed Interface Devices

Conventional simulation methods for Charged Device Model (CDM) peak current estimation, based on separate tester and IC lumped-element models, fail to capture fast transient phenomena at ultra-high-speed interfaces. A more comprehensive modeling approach, including on-die and package distributed parasitics, yields better predictive capabilities with respect to CDM qualification test results.

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Publication Details

Published
2024-09-16
DOI
https://doi.org/10.23919/eos/esd61719.2024.10702134
Citations
2
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
0.42
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article

System CDM Modeling for High-Speed Interface Devices

K. Domański, Brett Carn, Jian Gong, Ralf Brederlow et al.
2 citations
3D IC and TSV technologies
0.42
article

System CDM Modeling for High-Speed Interface Devices

K. Domański, Brett Carn, Jian Gong, Ralf Brederlow, Harald Goßner, V. Zia, Emanuele Groppo, Raj Dua
article en
2 citations

Abstract

Conventional simulation methods for Charged Device Model (CDM) peak current estimation, based on separate tester and IC lumped-element models, fail to capture fast transient phenomena at ultra-high-speed interfaces. A more comprehensive modeling approach, including on-die and package distributed parasitics, yields better predictive capabilities with respect to CDM qualification test results.

Intel (United States) (US), Intel (Germany) (DE), Mission College (US), Technical University of Munich (DE)
Affordable and clean energy
Openalex Percentile: Top 37%
3D IC and TSV technologies
0.42
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