System CDM Modeling for High-Speed Interface Devices
Conventional simulation methods for Charged Device Model (CDM) peak current estimation, based on separate tester and IC lumped-element models, fail to capture fast transient phenomena at ultra-high-speed interfaces. A more comprehensive modeling approach, including on-die and package distributed parasitics, yields better predictive capabilities with respect to CDM qualification test results.
Authors
- K. Domański (ORCID: https://orcid.org/0000-0002-9741-0588)
- Brett Carn
- Jian Gong (ORCID: https://orcid.org/0000-0001-5786-713X)
- Ralf Brederlow (ORCID: https://orcid.org/0000-0002-8118-757X)
- Harald Goßner (ORCID: https://orcid.org/0000-0002-6280-3613)
- V. Zia
- Emanuele Groppo
- Raj Dua
Institutions
- Intel (United States) (US)
- Intel (Germany) (DE)
- Mission College (US)
- Technical University of Munich (DE)
Publication Details
- Published
- 2024-09-16
- DOI
- https://doi.org/10.23919/eos/esd61719.2024.10702134
- Citations
- 2
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.42