Design Guidelines of Multibridge Channel-Ferroelectric FET for 3-nm Node and Beyond

Multibridge channel-ferroelectric field-effect transistor (MBC-FeFET) with metal-ferroelectric-metal-insulator-silicon (MFMIS) gate-stack is an advanced noble memory device, which is compatible with a 3-nm node technology logic device. Thanks to the wide effective channel width of the device’s stacked nanosheet (NS), the capacitance ratio of the interfacial layer (IL) and ferroelectric layer (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {IL}}$ </tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${C}_{\text {FE}}$ </tex-math></inline-formula>) can be maximized without area penalty, significantly improving memory window (MW) and endurance characteristics. In this work, we developed analytical compact models of memory characteristics for MFMIS gate-stack-based MBC-FeFET. Also, using this model, the gate-stack design guidelines were presented. As a result, the MW becomes three times larger, and the electric field in the IL layer (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {IL}}$ </tex-math></inline-formula>) becomes 0.17 times smaller after optimization. This is 21 times larger MW compared to a planar FeFET with initial gate-stack parameters applied.