On-Chip ESD Protection for Multi-Gbps Automotive Serial IO in a 16-nm FinFET Process

This work presents an on-chip ESD protection architecture for high-speed automotive SerDes receivers. The ESD protection, composed of primary, secondary and auxiliary clamps, is designed to withstand system-level ESD stress. The primary protection is provided by a bidirectional SCR that can sink 15 A of 100-ns TLP current. Impedance matching and bandwidth extension are achieved by integrating the ESD protection with a T-coil circuit.