Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology

A single event latch-up (SEL) rate prediction methodology for CMOS logics is proposed. The SEL failure rates at varied operating voltage and temperature can be predicted via the extraction of design and process parameters. The proposed methodology is implemented in bulk FinFET technology, and the prediction shows high consistency with experimental results within 90% statistical confidence. SEL impact analysis is realized by decoupling design- and process-related factors to enable SEL design-technology cooptimization (DTCO).