On the Practicality of Hardware Acceleration for Lightweight Block Ciphers

The Internet of Things (IoT) is prompting a shift in encryption for resource-constrained devices, such as sensor nodes and embedded systems. Such devices may not have enough power or computing capabilities to implement the same encryption algorithms that general-purpose computers use. Would these IoT devices benefit from having a dedicated chip perform the encryption? When another device does the encryption process by implementing logic gates in hardware, it is known as hardware acceleration. This paper studies practical considerations for implementing lightweight cipher algorithms in a field programmable gate array (FPGA) for the purpose of hardware acceleration. To do this, we implement different ciphers and the logic to have them interface with a microcontroller using serial communications. With concentration on the ISO/IEC 29192–2 standard, this paper shows the results for PRESENT, LEA, and CLEFIA ligthweight ciphers, where AES is used as a benchmark. Results show that PRESENT-128 and LEA-128 are the most efficient ciphers in terms of throughput and implementation area.