Design of a high-speed and adjustable CTLE circuit

The Continuous Linear Time Equalizer (CTLE) is suitable for wireline communications, and the CTLE has the characteristics of simple structure, low power consumption, and high-frequency component of the compensation signal, which is of great significance for different channel attenuation and high-bandwidth, low-power consumption, and adjustable balance. In this paper, a new tail current source circuit is designed in the negative capacitance, the negative capacitance tail current source is changed, and the position of the zero pole of the circuit is changed to achieve peak adjustability. The CTLE load adopts a passive inductor structure to weaken the capacitive characteristics of the circuit, ensure that the position of the pole is at high frequency, and expand the circuit bandwidth. The CTLE is implementedby28nm CMOS process, the core area of the layout is 177um×340um, and the simulation shows that the gain at 23GHzisadjustable in the range of 7.6dB to 15.4 dB at 1.2V supply voltage, and the maximum power consumption is 20.4mW.