A 0.0375-pJ/bit Charge-Steering Based Hybrid for 8-Gb/s/pin Full-Duplex Chip-to-Chip Interconnects in 65-nm CMOS

This paper presents an energy-efficient, half-rate charge-steering logic (HR-CSL) based echo cancellation hybrid (ECH) circuit topology for full-duplex(FD) signaling across chip-to-chip interconnects. The proposed charge-steering logic (CSL) based hybrid has much lower power consumption compared to conventional current-mode logic (CML) and voltage-mode logic (VML) based hybrid implementations, thanks to the discrete nature of CSL hybrid topology avoiding direct current path between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{DD}$ </tex-math></inline-formula> and ground. The prototype test chip design of the proposed hybrid circuit topology has been fabricated in 65 nm CMOS for a 20 cm FR4 PCB chip-to-chip interconnect with a supply voltage of 1.2 V. The measurement performance of the HR-CSL based hybrid circuit achieves 8 Gb/s FD operation at a power consumption of only 0.15 mW with an energy efficiency of 0.0375 pJ/bit. The measurement results show that the proposed hybrid circuit has a differential received signal voltage swing of 110 mV at 8 Gb/s data rate with a timing jitter of 20 ps. The proposed hybrid has a clock phase margin of 25% UI at bit-error-rate (BER) less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-12}$ </tex-math></inline-formula>. The active area of the hybrid is 0.0007 mm2.