Interrelation of Gate Resistance and Emitter/Source Inductance Impact on Inductive Load Phase-Leg Crosstalk

Crosstalk poses a significant concern in power electronics converters that incorporate a phase-leg structure. The detrimental impact of crosstalk can result in device malfunction or failure. In this article, a model of the phase-leg structure emphasizing parasitic elements is introduced. Subsequently, the mathematical model of the circuit is deduced, followed by an investigation into the impact of low-side insulated gate bipolar transistor (IGBT) gate resistance and the sensitivity of low-side switch emitter inductance. We explored in this article that in the inductive load switching a negative spike also happens in the lower device gate terminal during the crosstalk prior to the positive spike. This negative spike can be harmful for the gate oxide insulator of the device. For optimal outcomes, a double-pulse test is set up. This test entails the application of two closely spaced voltage pulses to a device, allowing the assessment of its switching characteristics in inductive loads. Furthermore, while examining the impact of low-side device gate resistance on crosstalk, the influence of low-side switch parasitic emitter inductance becomes evident, and the optimal values for these parameters are determined. The model is generic and applicable to any IGBT or power <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>, because crosstalk happens during turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> process which the turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> model of both devices is similar, with the specific case study in this article being the IXGH60N60C2 and IRFP460.