Channel Trimming Process to Improve Electro-Thermal Characteristics for Sub-3-nm Node Si Nanosheet FETs

This study examined the electrical and thermal behaviors of nanosheet (NS) field-effect transistors (NSFETs) with trimmed channels using a technology computer-aided design (TCAD) simulation. NSFETs are expected to exhibit excellent electrical behaviors owing to thin gate-all-around (GAA) channels. However, NSFETs still suffer from: 1) high punchthrough current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {PTS}}$ </tex-math></inline-formula>) in the punchthrough stopper (PTS) region and 2) poor heat dissipation by the thin channel thickness. Thus, to resolve these problems, this study proposed NSFETs with trimmed NS channels and a trench gate in the PTS region. This structure can be formed via the deposition of thick silicon layers during Si/SiGe stacking and consequently trimming the silicon regions (NS channels, PTS region) following the channel release. Consequently, the trench gate strengthened the gate controllability for the PTS region, exhibiting remarkable <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {PTS}}$ </tex-math></inline-formula> suppression. In addition, untrimmed thick channel ends improved heat transfer, whereas the trimmed channel centers provided excellent gate controllability. Therefore, the trimming process, which formed trimmed channels and a trench gate, is expected to simultaneously solve the inherent electrical and thermal issues encountered in NSFETs.