Simplified Oblique Decision Tree Accelerator

In recent years, hardware platforms like field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) are highly preferred for implementing machine learning algorithms in low-power or high-speed applications. This letter proposes a simplified oblique node decision tree algorithm. The classification is implemented on FPGA and ASIC for activity recognition and Parkinson’s tremor detection. A mode number is used to choose the application mode. To provide better classification performance, efficient multiplier-less architectures have been used for power efficiency. This design operates at a maximum frequency of 167 MHz and has the lowest latency as compared to the existing hardware. It is also found to have very low resource consumption as compared to other existing high-speed architectures.