A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC

This article presents a fractional-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> digital-to-time converter (DTC)-based digital phase-locked loop (PLL), achieving simultaneously low phase noise and low spurious tones. The PLL adopts a novel DTC circuit, denoted as reverse-concavity variable-slope (VS), which breaks the tradeoff between power consumption, phase noise, and linearity, which is typical of conventional VS-DTCs. A dedicated digital algorithm, working in the background of the PLL, is introduced to minimize DTC nonlinearity. The PLL prototype, fabricated in 28-nm bulk CMOS, has an active area of 0.21 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and dissipates 17.5 mW. At the near-integer channel around 8.75 GHz, it shows a worst case fractional spur of −63.4 dBc and an integrated rms jitter of 57.3 fs, including spurs. This results in a power-jitter figure of merit of −252.4 dB.