Elevated-Epi (Elepi) Technique for 3D IC With Stacked FinFETs, Interlevel Metal, and 25×33 mm<sup>2</sup> Single-Crystalline Silicon on SiO<sub>2</sub>
The elevated-epi technique (EET) is introduced for fabricating single-crystal (100) silicon of wafer field size (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times 33$ </tex-math></inline-formula> mm) for monolithic 3-D integrated circuits (3D ICs) using a low substrate temperature pulse laser method. This method enables the demonstration of 3-D inverters with interlayer metal M0 positioned between two layers of FinFETs. Additionally, a hybrid-3-D cell library is presented to enhance the performance, power, and area (PPA) of 3D IC. This hybrid-3-D cell library is crucial in design-technology co-optimization, significantly improving PPA metrics for advanced 3D IC applications.
Authors
- Chiao-Yen Wang
- Nein-Chih Lin
- Bo-Jheng Shih (ORCID: https://orcid.org/0009-0009-7037-0844)
- Hung-Ming Chen (ORCID: https://orcid.org/0000-0001-8173-3131)
- Kuan‐Neng Chen (ORCID: https://orcid.org/0000-0003-4316-0007)
- Po-Tsang Huang (ORCID: https://orcid.org/0000-0001-8679-2755)
- Yu-Ming Pan
- Chang-Hong Shen
- Chenming Hu
- Chih-Chao Yang
- I-Chun Hsieh
- Huang‐Chung Cheng
- Huan-Yu Chiu
- Hao-Tung Chung
- Chieh-Ling Lee
Institutions
- National Yang Ming Chiao Tung University (TW)
- Taiwan Semiconductor Manufacturing Company (Taiwan) (TW)
- National Institutes of Applied Research (TW)
Publication Details
- Journal
- IEEE Transactions on Electron Devices
- Published
- 2024-10-07
- DOI
- https://doi.org/10.1109/ted.2024.3460763
- Citations
- 1
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.21