Implementation of the Sigmoid Function on Current FPGAs Using the Bit-Level Mapping Method

The sigmoid function is one of the most frequently used activation functions in neural networks. When implementing neural networks on FPGAs, the bit-level mapping method is effective in reducing computational costs. This method allows computing using combinational logic only, without adders and multipliers. In addition, the bit-level method provides less computational error compared to approximations. In this paper, the authors consider three circuits that can be implemented on FPGAs to compute the sigmoid function using the bit-level mapping method. These circuits have been implemented on the typical FPGA programmable logic: LUTs, multiplexers, and carry-chains. One of the circuits uses LUTs only, and another one - LUTs and general-purpose multiplexers. These two circuits have been described in the behavioral style and synthesized. The third circuit uses LUTs and carry-chain multiplexers, and it has been described in the structural style. The circuits have been compared in terms of data path delays, area requirements, and applicability for the cases of different bit widths.