Image Processing on the Edge using an Entry-Level FPGA

This paper explores the application of FPGA programmable structures in the field of digital image signal processing (ISP). FPGAs offer high flexibility, speed and parallelism, making them ideal for general digital signal processing (DSP), as well as specific ISP tasks. The paper utilizes standard ISP algorithms such as morphological operations, filtering and edge detection to compare practical implementations of FPGA and CPU-based compute engines. Through illustrative examples and empirical results, we demonstrate the distinct advantages of employing FPGA for these use-cases, and contrast them with traditional CPU approaches, clearly showing FPGA capacity to significantly accelerate execution. The challenges that arise from resource-limited IOT-class hardware configurations are highlighted in the paper, namely resource optimization, memory management and maximal frequency.

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Publication Details

Published
2024-09-16
DOI
https://doi.org/10.1109/elmar62909.2024.10694571
Primary Topic
CCD and CMOS Imaging Sensors
Type
article
Field-Weighted Citation Impact
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article

Image Processing on the Edge using an Entry-Level FPGA

Emir Sokić, Nedim Osmić, Almir Salihbegović, Armin Zunic et al.
CCD and CMOS Imaging Sensors
article

Image Processing on the Edge using an Entry-Level FPGA

Emir Sokić, Nedim Osmić, Almir Salihbegović, Armin Zunic, Isam Vrce
article en

Abstract

This paper explores the application of FPGA programmable structures in the field of digital image signal processing (ISP). FPGAs offer high flexibility, speed and parallelism, making them ideal for general digital signal processing (DSP), as well as specific ISP tasks. The paper utilizes standard ISP algorithms such as morphological operations, filtering and edge detection to compare practical implementations of FPGA and CPU-based compute engines. Through illustrative examples and empirical results, we demonstrate the distinct advantages of employing FPGA for these use-cases, and contrast them with traditional CPU approaches, clearly showing FPGA capacity to significantly accelerate execution. The challenges that arise from resource-limited IOT-class hardware configurations are highlighted in the paper, namely resource optimization, memory management and maximal frequency.

University of Sarajevo (BA)
Openalex Percentile: Top 85%
CCD and CMOS Imaging Sensors
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