A Compact CMOS Broadband Single-Sideband Time Modulator Based on 4-bit Vector-Sum Phase Shifter

A compact CMOS broadband single-sideband time modulator (SSBTM) is presented. The proposed SSBTM is based on a periodically controlled 4-bit passive vector-sum phase shifter (VSPS) to realize high precision phase shifting, high sideband rejection and low amplitude variation. The SSBTM uses particular-sized cells to reduce impedance changes in state switching. Additionally, the 8-bit control sequences are generated by using a true-single-phase-clock (TSPC) divide-by-16 frequency divider which is controlled by 1-bit square wave control signal. The SSBTM is designed in 55-nm CMOS technology with a layout area of 0.83 × 0.54 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The simulated results show that sideband suppression ratio (SSR) is −23.8 dBc, the power consumption is 15.6 mW from the 1.2 V supply, and its gain is −5.2±1.3 dB. In the frequency band of 1−4.5 GHz, the phase resolution can reach more than 10-bits, RMS phase error is 0.1∼0.2°, maximum gain error is less than 0.02 dB.

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Published
2024-08-16
DOI
https://doi.org/10.1109/aces-china62474.2024.10700003
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
Field-Weighted Citation Impact
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article

A Compact CMOS Broadband Single-Sideband Time Modulator Based on 4-bit Vector-Sum Phase Shifter

L. Wang, Guoxiao Cheng, Qi Ma, Tao Wang
Advancements in PLL and VCO Technologies
article

A Compact CMOS Broadband Single-Sideband Time Modulator Based on 4-bit Vector-Sum Phase Shifter

L. Wang, Guoxiao Cheng, Qi Ma, Tao Wang
article en

Abstract

A compact CMOS broadband single-sideband time modulator (SSBTM) is presented. The proposed SSBTM is based on a periodically controlled 4-bit passive vector-sum phase shifter (VSPS) to realize high precision phase shifting, high sideband rejection and low amplitude variation. The SSBTM uses particular-sized cells to reduce impedance changes in state switching. Additionally, the 8-bit control sequences are generated by using a true-single-phase-clock (TSPC) divide-by-16 frequency divider which is controlled by 1-bit square wave control signal. The SSBTM is designed in 55-nm CMOS technology with a layout area of 0.83 × 0.54 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The simulated results show that sideband suppression ratio (SSR) is −23.8 dBc, the power consumption is 15.6 mW from the 1.2 V supply, and its gain is −5.2±1.3 dB. In the frequency band of 1−4.5 GHz, the phase resolution can reach more than 10-bits, RMS phase error is 0.1∼0.2°, maximum gain error is less than 0.02 dB.

Nanjing University of Science and Technology (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 85%
Advancements in PLL and VCO Technologies
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