Secure SRAM Memory Design for Secret Data Protection Against Data Imprinting and Power Attack

SRAM is crucial in cryptographic devices for temporarily storing secret keys used in encryption and decryption. However, conventional 6T SRAM cells are vulnerable to side-channel attacks (SCA) via power consumption analysis, as writing the same and opposite data consumes unequal power. Additionally, the Negative Bias Temperature Instability (NBTI) effect in PMOS transistors introduces a data imprinting attack, where attackers exploit differences in the relative strength of pull-up transistors, affecting the threshold voltage ([Formula: see text], noise margin (SNM), and delay of the SRAM cell, to retrieve stored data. To address these vulnerabilities, a new SRAM cell design is proposed, incorporating a loop cutting technique to prevent SCA and data toggling behavior to mitigate the data imprinting attack. Monte Carlo simulations of power dissipation during various write operations show that the proposed cell achieves a secure write operation with a maximum overlap of 96.87%. The loop cutting technique reduces power dissipation by 1.54 times and write operation time by 1.44 times compared to the conventional 6T SRAM cell. The stress factor (SF) is also calculated to measure the stress on storage nodes over time. The SF for the 6T SRAM cell is 2.34 after 180 min, while the data toggling approach in the proposed SRAM cell achieves an SF of 0.72, effectively preventing the data imprinting effect. The introduction of transmission gates increases the area overhead of the proposed cell by 1.88[Formula: see text]. All simulations are conducted using the gpdk 90-nm technology file in Cadence Virtuoso.