Load-Independent Junction Temperature Estimation via Combined TSEPs Modeling for SiC MOSFETs
Junction temperature estimation with high precision is crucial to the reliability and safe operating of silicon-carbide (SiC) metal–oxide–semiconductor field-effect transistors (<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s). Approaches using temperature-sensitive electrical parameters (TSEPs) are widely employed in the monitoring, offering the benefits of noninvasiveness and fast thermal response. This article proposes a load-independent junction temperature model incorporating three TSEPs, the peak drain voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,pk</sub>), the peak drain current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,pk</sub>), and the turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> delay time (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d,on</sub>). This model eliminates the impact of both load voltage and current, thus improving the estimating accuracy and anti-interference ability compared with other approaches relying on single or fewer TSEPs. Initially, four typical TSEPs and their dependencies on junction temperature and load conditions are established theoretically. Then, the proposed modeling method via combined TSEPs is introduced. Its effectiveness and advantage are experimentally validated with double-pulse tests. Under various loading conditions, the conventional single TSEP method exhibits a mean absolute percentage error of up to 22.56%, whereas the proposed method effectively reduces it to 6.31%.
Authors
- Cungang Hu (ORCID: https://orcid.org/0000-0001-8767-6713)
- Xi Tang (ORCID: https://orcid.org/0000-0002-4479-4485)
- Kun Tan (ORCID: https://orcid.org/0000-0002-1591-2876)
- M. X. Luo (ORCID: https://orcid.org/0009-0006-4540-6049)
- Wenping Cao (ORCID: https://orcid.org/0000-0002-8133-3020)
- Bing Ji (ORCID: https://orcid.org/0000-0003-0034-6901)
- Zhaofu Zhang (ORCID: https://orcid.org/0000-0002-1406-1256)
- Zekun Li (ORCID: https://orcid.org/0000-0003-1763-7190)
Institutions
- Anhui University (CN)
- University of Leicester (GB)
- Wuhan University (CN)
Publication Details
- Journal
- IEEE Transactions on Power Electronics
- Published
- 2024-10-03
- DOI
- https://doi.org/10.1109/tpel.2024.3473529
- Citations
- 8
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 1.67
Funders
- National Natural Science Foundation of China
- Natural Science Foundation of Anhui Province