Load-Independent Junction Temperature Estimation via Combined TSEPs Modeling for SiC MOSFETs

Junction temperature estimation with high precision is crucial to the reliability and safe operating of silicon-carbide (SiC) metal–oxide–semiconductor field-effect transistors (<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s). Approaches using temperature-sensitive electrical parameters (TSEPs) are widely employed in the monitoring, offering the benefits of noninvasiveness and fast thermal response. This article proposes a load-independent junction temperature model incorporating three TSEPs, the peak drain voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,pk</sub>), the peak drain current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,pk</sub>), and the turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> delay time (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d,on</sub>). This model eliminates the impact of both load voltage and current, thus improving the estimating accuracy and anti-interference ability compared with other approaches relying on single or fewer TSEPs. Initially, four typical TSEPs and their dependencies on junction temperature and load conditions are established theoretically. Then, the proposed modeling method via combined TSEPs is introduced. Its effectiveness and advantage are experimentally validated with double-pulse tests. Under various loading conditions, the conventional single TSEP method exhibits a mean absolute percentage error of up to 22.56%, whereas the proposed method effectively reduces it to 6.31%.

Authors

Institutions

Publication Details

Journal
IEEE Transactions on Power Electronics
Published
2024-10-03
DOI
https://doi.org/10.1109/tpel.2024.3473529
Citations
8
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
Field-Weighted Citation Impact
1.67

Funders

Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Load-Independent Junction Temperature Estimation via Combined TSEPs Modeling for SiC MOSFETs

Cungang Hu, Xi Tang, Kun Tan, M. X. Luo et al.
8 citations
IEEE Transactions on Power Electronics
Silicon Carbide Semiconductor Technologies
1.67
article

Load-Independent Junction Temperature Estimation via Combined TSEPs Modeling for SiC MOSFETs

Cungang Hu, Xi Tang, Kun Tan, M. X. Luo, Wenping Cao, Bing Ji, Zhaofu Zhang, Zekun Li
article en
8 citations

Abstract

Junction temperature estimation with high precision is crucial to the reliability and safe operating of silicon-carbide (SiC) metal–oxide–semiconductor field-effect transistors (<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small>s). Approaches using temperature-sensitive electrical parameters (TSEPs) are widely employed in the monitoring, offering the benefits of noninvasiveness and fast thermal response. This article proposes a load-independent junction temperature model incorporating three TSEPs, the peak drain voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,pk</sub>), the peak drain current (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,pk</sub>), and the turn-<sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</small> delay time (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d,on</sub>). This model eliminates the impact of both load voltage and current, thus improving the estimating accuracy and anti-interference ability compared with other approaches relying on single or fewer TSEPs. Initially, four typical TSEPs and their dependencies on junction temperature and load conditions are established theoretically. Then, the proposed modeling method via combined TSEPs is introduced. Its effectiveness and advantage are experimentally validated with double-pulse tests. Under various loading conditions, the conventional single TSEP method exhibits a mean absolute percentage error of up to 22.56%, whereas the proposed method effectively reduces it to 6.31%.

IEEE Transactions on Power ElectronicsVol. 40(1)
Anhui University (CN), University of Leicester (GB), Wuhan University (CN)
National Natural Science Foundation of China, Natural Science Foundation of Anhui Province
Affordable and clean energy
Openalex Percentile: Top 15%
Silicon Carbide Semiconductor Technologies
1.67
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.