A Sub-10-ps Resolution Multichannel Time-to-Digital Converter With Two-Stage Interpolation for High-Energy Physics Applications

This article presents the design of a sub-10-ps resolution 16-channel time-to-digital converter (TDC) for high-energy physics applications. The architecture is based on a coarse counter and a two-stage interpolator. Dual 12-bit gray counters are employed to record the timestamp for coarse conversion extending the measurement dynamic range, while the interpolator is designed with a coarse-fine structure for fine conversion. The first interpolation stage is implemented with a multiphase delay line with a resolution of 89 ps, while the second interpolation stage is achieved with a Vernier delay line with a subgate-delay resolution of 7 ps. A low-jitter compact multiplying delay-locked loop (MDLL) generates an 800-MHz internal clock signal out of 50-MHz external reference clock, which shrinks the number of delay elements to cover one period of the coarse clock. Operation at higher frequency also provides high throughput and short conversion time. A new differential delay cell and a phase detector composed of phase-frequency detector and bang-bang phase detector (BBPD) are proposed in the delay-locked loop (DLL) design to reduce the nonlinearity. The TDC offers a measurement range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.12~\mu $ </tex-math></inline-formula>s and 7-ps resolution. Fabricated in a 1.8-V 180-nm CMOS process, the chip occupies a die size of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.2\times 2.2$ </tex-math></inline-formula> mm. The measured single-shot precision (SSP) is better than 7.5 ps, while the total static power consumption is 140 mW for 16 channels and the dynamic power consumption is approximately 6.5 mW/MHz/channel.