Analysis of Logic Synthesis Results with various Technology Nodes for RISC-V Design

This study investigates the synthesis process of a RISC-V processor with varying technology nodes ($14 \mathrm{~nm}, 32 \mathrm{~nm}$, and 90 nm) and clock periods ranging from 0 to 5 nanoseconds. The problem statement is to address the limited availability of processor designs using the RISC-V ISA in undergraduate study, even though the RISC-V community is growing rapidly. This shortage is due to the relatively recent development of the ISA. The analysis initiates by considering design constraints, such as clock frequency, area limitations, and timing requisites specific to each technology node. Utilizing the Design Compiler tool, the Register Transfer Level (RTL) description of the RISC-V processor is transformed into a gate-level netlist. Performance metrics including clock period requirements, and slack margins across technology nodes are scrutinized. Power consumption of the processor is assessed at various clock intervals to gain insights into its power profile. Additionally, to enhance designs for each technology node, processor area consumption is thoroughly examined. This paper delineates an approach applicable to VLSI design courses at the undergraduate level.