Source-Drain Series Resistance Model for <i>N</i>-Stack Nanosheet FETs Using Transmission Line Matrix Method

The continuous scaling of gate length as well as source and drain (S/D) area increases the parasitic S/D series resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {sd}}$ </tex-math></inline-formula> and decreases the channel resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {ch}}$ </tex-math></inline-formula>. As a result, the contribution of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$R_{\text {sd}}$ </tex-math></inline-formula> to the total source-to-drain series resistance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {tot}}$ </tex-math></inline-formula> increases, which decreases the percentage voltage drop across the channel. As a result, the drain drive current degrades at a higher gate bias. The increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {sd}}$ </tex-math></inline-formula> increases power dissipation, thermal noise, and delay and reduces the maximum frequency of the device. Therefore, accurate models for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {sd}}$ </tex-math></inline-formula> are needed for optimizing the device geometry to improve its performance and estimate the figure of merits, accurately. The analytical model for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {sd}}$ </tex-math></inline-formula> in nanosheet FET (NSFET) to capture the impact of current distribution in different vertically stacked nanosheet (NS) channels is still elusive in the literature. To this end, we have developed an analytical model for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {tot}}$ </tex-math></inline-formula>, which includes both <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {sd}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {ch}}$ </tex-math></inline-formula> of the N-stack NSFETs, using the transmission line matrix (TLM) method for the first time. The TLM method effectively captures the effect of current distribution in the S/D region and each of the vertically stacked NS channels in N-stack NSFET. The results obtained from the developed model for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {tot}}$ </tex-math></inline-formula> show good agreement with the simulation results validating the TLM method.