Optimization of electrical phase change memory for in-memory computing

Among the emerging approaches for deep neural network (DNN) acceleration, analog in-memory computing (AIMC) emerges as a promising solution by directly performing computations within crossbar arrays of non-volatile memories (NVMs), using the device conductance values to represent the weight. Phase change memory (PCM) is one of the most promising NVMs for AIMC particularly for inference using previously trained DNN weights. However, the utilization of PCMs for analog computing introduces nonidealities, including resistance drift, read noise, limited memory window, and various device failures. I will discuss our work on optimizing PCM devices to alleviate these nonidealities and mitigate their impact on AIMC.