Lightweight Active Fences for FPGAs

The use of active fences has been proposed as a protection against remote power analysis attacks. This counter-measure relies on reserving a reconfigurable space within the FPGA which will separate it into sub-regions. These “fences” will then generate some electrical interference to hinder the performance of an attack. As FPGAs can be configured in multiple ways, there are different approaches for connecting the hardware inside the fence. In this work, we describe a LUT-based configuration which can achieve the same instantaneous power drop as a ring oscillator bank with less LUTs. This contributes to reducing the hardware costs of active fences.