A New Carry Look-Ahead Adder Architecture Enabling Improved Speed and Energy Efficiency

We present a new carry look-ahead adder (NCLA) architecture that makes use of non-uniform-size CLA modules in contrast to the existing CLA architecture which typically makes use of uniform-size CLA modules. This helps to achieve improved speed and energy efficiency for the NCLA architecture compared to the existing CLA architecture without incurring notable area and power penalties. To demonstrate the advantage of NCLA, several adders were implemented ranging from the slow ripple carry adder to the generally considered fastest parallel-prefix adder viz. the Kogge-Stone adder (KSA), and their performance metrics were compared. The 32-bit addition was considered an example, and the different adders were implemented in a semi-custom design method using a 28-nm CMOS standard digital cell library. Based on the synthesis results, the NCLA was found to facilitate significant optimizations in design metrics compared to its high-speed counterparts. To give some examples, the NCLA achieved: (i) a 14.7% reduction in delay and a 13.4% reduction in energy compared to a high-speed CLA while occupying slightly more area, (ii) a 42.1% reduction in delay and a 58.3% reduction in energy compared to a conditional sum adder while occupying 8% more area, (iii) a 14.7% reduction in delay and a 37.7% reduction in energy compared to a speed-optimized carry select adder while requiring 37% less area, and (iv) a 20.2% reduction in energy and a 55.4% reduction in area compared to the KSA.