HDL Code Variation: Impact on FPGA Performance Metrics and CAD Tools

With the proliferation of utilizing FPGAs for hardware designs across various application domains, the interpretive role that the CAD tools play in the implementation of these FPGA-based designs is coming under increased scrutiny. Also, with the increasing design complexity, evermore abstraction has been placed between the HDL designer and the CAD interpreter. While CAD tools are designed to optimize FPGA-based designs, in this research work, we demonstrate that CAD tools are susceptible to differences in HDL coding style; hence, minor differences in HDL constructs/codes can lead to significantly different final hardware implementations. This in turn impacts final area usage, speed, and power consumption. Using a simple hardware decoder, we illustrate and analyze the changes caused by entering differing code styles into the CAD tool for implementation. Our experimental results show that minor changes in code style can significantly affect all metrics on final implementation without changing the functionality of the circuit.