0.765-FJ/Bit/Search Content Addressable Memory Using Search Line Pre-Charge-Free (SLPF) Scheme

Content Addressable Memories (CAMs) are high-speed hardware lookup tables that are crucial in routing, packet classification, search, and other fast look-up applications. Despite having the advantage of high speed, they have limitations due to their power hungriness. This paper addresses the limitations of existing CAMs with two novel modifications in the proposed Search Line Pre-Charge-Free Low-Power-Content Addressable Memory (SLPFCAM) structure. The first novelty is their gated evaluation matching circuit and the second is a match line pre-charge controller. The proposed design reduces the energy consumption and improves the speed of the CAM by eliminating the SLprecharge phase in the CAM operation. The pre-charge controller prevents the attempt of match line pre-charge when it is not required. The design has been implemented using Cadence Virtuoso in a 90-nm CMOS technology with 1-V supply, and the post-layout simulation results show that the SLPFCAM makes significant improvements with a minimum of 83% less power consumption, a 91% less search delay, and the average energy consumption being 0.765 fJ/bit/search.