Design and implementation of branch prediction based on LoongArch

A branch prediction scheme for the LoongArch five-stage pipeline architecture is proposed. This scheme is compatible with cache-equipped designs, predicting the branch direction and target address of branch instructions after fetching them from the high-speed cache during the instruction fetch stage. It can recover from branch prediction failures while ensuring the correct execution of the instruction pipeline. After software simulation and FPGA board testing, this scheme meets the design requirements, has high prediction efficiency, and can significantly enhance the performance of the LoongArch five-stage pipeline CPU.