Analysis and Design of Wideband GaAs Digital Step Attenuators

This brief analyses the causes of amplitude and phase errors in digital step attenuators (DSAs), and proposes two novel structures, namely, the series inductive compensation structure (SICS) and the small-bit compensation structure, to reduce these two kinds of errors. A 6-bit DSA with ultrawideband, low insertion loss, and high accuracy is presented, which has an area of only 0.51 mm2 and shows an attenuation range of 31.5 dB in 0.5 dB steps. Measurements reveal that the root-mean-square (rms) amplitude and phase errors for the 64 attenuation states are within 0.18 dB and 8°, respectively. The insertion loss is better than 2.54 dB, and the input 1 dB compression point (IP1 dB) is better than 29 dBm. To the best of our knowledge, this chip presents the highest attenuation accuracy, the lowest insertion loss, the best IP1 dB, and a good matching performance in the range of 2–22 GHz using the 0.25-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m GaAs p-HEMT process.